For the purpose of more adequately describing a technological level for the present invention at present, all descriptions of the patents, patent applications) patent gazettes, scientific papers, and the like which are cited or specified in tho present application will be incorporated herein by reference.
A printed circuit board comprises electronic components such as IC and LSI, and signal wiring for connecting those components, and is mounted on an almost every equipment as the heart of electronic equipment. A multilayer printed circuit board includes a power line composed of aground wiring for providing reference potential of power supply wiring and a circuit for supplying a direct-current voltage required for the IC and the LSI to operate and the potential variation of the power line at high frequency often triggers the generation of IC and LSI malfunction, and high levels of unnecessary electromagnetic wave radiation.
The most commonly adopted technique to control the potential variation of the power line is a method by which a capacitor is mounted on the surface of a board to connect both ends thereof to power supply and ground for absorbing voltage variation.
For example, in a design method of a printed circuit board, a printed circuit board, and electronic equipment provided with a printed circuit board, in order to mount an electronic circuit element on a two-layer printed wiring board 81 in which a printing circuit pattern is formed on a surface (FIG. 1A) and a back surface (FIG. 1B) through an insulated base 80 as shown in FIG. 1A and FIG. 1B, there is adopted structure in which an inductance pattern is formed in a manner that a land is disposed on the surface, a ground pattern 84 up to an inner site of the electronic circuit element is disposed, a trunk power source pattern 82 of a trunk is disposed, a power source branching pattern 83 is branched off from the trunk power source pattern, extended up to the inner site of the electronic circuit element, and connected to a part of the land via a through hole 85, and an inductance formed between the power source branching pattern and the trunk power source pattern is larger than an inductance formed between the power source branching pattern and a capacitor disposed in the vicinity of the power source branching pattern 83. This prior art is disclosed in the Japanese Unexamined Patent Publication No. 9(1997)-54788, Paragraph Number “0032” to “0034,” and FIG. 1.
Additionally, as shown in FIG. 2A, FIG. 2B, and FIG. 2C, in power supply pattern connecting structure of an electronic circuit component provided with wiring patterns which are connected to each of both terminals of a power source pin 93 and a ground pin 94 of an LSI 92 mounted on a printed wiring board 91, and which are made up of first power supply patterns 97 and 98, and first ground patterns 99 and 100 for flowing a supply current from a power supply layer (power plane) 95 and a ground layer (ground plane) 96, and a capacitor 101 which is connected to the two wiring patterns and mounted on the same printed circuit board or the back surface thereof as the LSI 92, there is adopted structure in which the power supply layer 95 is connected to a second power supply pattern provided at one end of the capacitor 101 through a via hole 103, and a ground layer is connected to the first ground patterns 99 and 100 through a via hole 104. This prior art is disclosed in the Japanese Unexamined Patent Publication No. 2000-156548, Paragraph Number “0005” and FIG. 1.
Moreover, most printed circuit boards are designed with the use of a CAD (Computer Aided Design) system at present. There is proposed a system that the CAD system is effectively utilized to automatically dispose a capacitor in a design stage of a printed circuit board.
For example, a printed board arranging processor is provided with an input part 111, an arithmetic processing part 112, a data storage part 113, and an arranging processing part 114, as shown in FIG. 3. IC to which a capacitor is to be added is retrieved in an objective IC retrieval part 116 in the arranging processing part 114 based on a capacitor addition condition inputted in a bypass capacitor addition condition input part 115 through the input part 111, and the capacitor is automatically added to the IC retrieved in the objective IC retrieval part 116 based on the capacitor addition condition inputted through the input part 111 in a bypass capacitor automatic addition part 117 only by inputting the condition without a manual operation. This prior art is disclosed in the Japanese Unexamined Patent Publication No. 2000-99560, Paragraph Number “0017” and FIG. 1.
A radiation noise prevention printed board arranging and wiring processing system is also provided with an input/output unit 120, an input part 121, an arithmetic processing part 122, a data storage part 123, and an arranging and wiring processing part 124, as shown in FIG. 4. The arranging and wiring processing part 124 is further provided with an electronic component power source pin extraction part 125 for extracting a power source pin of an electronic component, a wiring pattern extraction part 126 for extracting a wiring pattern from the power source pin to a via hole of a power source, the line length of the extracted wiring pattern, a line length and line width inspection part 127 for inspecting the line length and line width of the extracted wiring pattern, a bypass capacitor addition possibility inspection part 128 for inspecting whether or not the addition of the capacitor is possible, a wiring route change possibility inspection part 129 for inspecting whether or not a wiring route capable of a capacitor addition is present in the case that the capacitor can be added in a present wiring route, a wiring route change execution part 130 for changing the wiring route, a bypass capacitor addition execution part 131, and an error display part 132 for performing error display in the case that the capacitor can not be added even when the wiring route is changed. This prior art is disclosed in the Japanese Unexamined Patent Publication No. 2000-35976, Paragraph Number “0009,” “0015,” and FIG. 1.
However, with the progress of high-density implementation, a case in which an LSI package and the like requiring high-density wiring called BGA (Ball Grid Array) is increased, leading to difficulty in realizing such mounting structure of the capacitors as shown in FIG. 1A, FIG. 1B, FIG. 2A, FIG. 2B, and FIG. 2C.
Additionally, in a case in which a capacitor is automatically added, it is impossible to determine whether or not the structure is best suited because the relationship between the position at which the capacitor is mounted and unnecessary electromagnetic wave radiation control or circuit malfunction prevention is not clearly defined.